This circuit design for a current-mode analog multiplier/ divider is based on current-controlled conveyors (CCCII) and a second-generation current conveyor (CCII). No passive components are used.

In this paper, design of 32-bit parallel multiplier is presented, by introducing Carry Save Adder (CSA) in partial product lines. The multiplier given in this paper is modeled using VHDL (Very High ...

Designed a 16 bit pipe-lined multiplier using the concept of partial products. DRC check and LVS match were performed. It was designed using cadence spectre with almost equal fall and rise delays.

A 2-bit booth encoder with Josephson Transmission Lines (JTLs) and Passive Transmission Lines (PTLs) is designed. The booth encoding method is one of the algorithms to obtain partial products. With ...

This frequency upconverter circuit is a simple alternative to doing period measurement or accepting long latency when measuring very low frequencies, on the order of one to 100 Hz. Due to the fact ...