EDN

Compact PCI” What’s next?

Compact Peripheral Component Interconnect platforms have a long history as host-controller topologies that use PCI bus H.110 buses to communicate with Internet telephony platforms. This was a good ...
Design-Reuse

Arteris Introduces P-NoC to Address SoC Peripheral Interconnect Requirements

Expansion of Pioneering NoC Technology Enables Efficient Integration of Peripheral Component IP with Core On-Chip Communications to Improve SoC Productivity and Margins SAN JOSE, Calif.--August 03, ...
Design-Reuse

PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions

The Peripheral Component Interconnect Express (PCIe) is a high-speed, serial, point to point computer expansion bus standard developed to supersede legacy interfaces such as PCI, PCI-X, and AGP.